at28lv010 1 megabit (128k x 8) low voltage paged cmos e 2 prom features single 3.3v 10% supply fast read access time - 200 ns automatic page write operation internal address and data latches for 128-bytes internal control timer fast write cycle time page write cycle time - 10 ms maximum 1 to 128-byte page write operation low power dissipation 15 ma active current 20 m a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology endurance: 100,000k cycles data retention: 10 years jedec approved byte-wide pinout commercial and industrial temperature ranges description the at28lv010 is a high-performance 3-volt only electrically erasable and program- mable read only memory. its 1 megabit of memory is organized as 131,072 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation of just 54 mw. when the device is deselected, the cmos standby current is less than 20 m a. (continued) pdip top view pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc dont connect pin configurations tsop top view plcc top view 0395a at28lv010 2-155
block diagram temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* the at28lv010 is accessed like a static ram for the read or write cycle without the need for external compo- nents. the device contains a 128-byte page register to al- low writing of up to 128-bytes simultaneously. during a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmels 28lv010 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. software data protection is implemented to guard against inadvertent writes. the de- vice also includes an extra 128-bytes of e 2 prom for de- vice identification or tracking. description (continued) 2-156 at28lv010
device operation read: the at28lv010 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention in their system. write: the write operation of the at28lv010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. each write operation must be preceded by the software data protection (sdp) command sequence. this sequence is a series of three unique write command operations that enable the internal write circuitry. the command sequence and the data to be written must conform to the software protected write cycle timing. addresses are latched on the falling edge of we or ce, whichever occurs last and data is latched on the rising edge of we or ce, whichever occurs first. each succes- sive byte must be written within 150 m s (t blc ) of the pre- vious byte. if the t blc limit is exceeded the at28lv010 will cease accepting data and commence the interal program- ming operation. if more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the a7 - a16 inputs. for each we high to low transition during the page write operation, a7 - a16 must be the same. the a0 to a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. data polling: the at28lv010 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit: in addition to data polling the at28lv010 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling be- tween one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection: if precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the at28lv010 in the follow- ing ways: (a) v cc power-on delay - once v cc has reached 2.0v (typical) the device will automatically time out 5 ms (typical) before allowing a write: (b) write inhibit - holding any one of oe low, ce high or we high inhibits write cy- cles; (c) noise filter - pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. software data protection: the at28lv010 in- corporates the industry standard software data protection (sdp) function. unlike standard 5-volt only e 2 proms, the at28lv010 has sdp enabled at all times. therefore, all write operations must be preceded by the sdp com- mand sequence. the data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. any attempt to write to the device without the 3-byte se- quence will start the internal timers. no data will be written to the device. however, for the duration of t wc , read op- erations will effectively be polling operations. at28lv010 2-157
mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. operating modes symbol parameter condition min max units i li input load current v in = 0v to v cc 1 m a i lo output leakage current v i/o = 0v to v cc 1 m a i sb v cc standby current cmos ce = v cc - 0.3v to v cc + 1v com. 20 m a ind. 50 m a i cc v cc active current f = 5 mhz; i out = 0 ma; v cc = 3.6v 15 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 3.0v .45 v v oh output high voltage i oh = -100 m a; v cc = 3.0v 2.4 v dc characteristics AT28LV010-20 at28lv010-25 operating temperature (case) com. 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c v cc power supply 3.3v 5% 3.3v 10% dc and ac operating range 2-158 at28lv010
AT28LV010-20 at28lv010-25 symbol parameter min max min max units t acc address to output delay 200 250 ns t ce (1) ce to output delay 200 250 ns t oe (2) oe to output delay 0 80 0 100 ns t df (3, 4) ce or oe to output float 0 55 0 60 ns t oh output hold from oe, ce or address, whichever occurred first 00ns ac read characteristics notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5 ns input test waveforms and measurement level output test load typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. at28lv010 2-159
symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 100 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 200 ns t ds data set-up time 100 ns t dh , t oeh data, oe hold time 10 ns note: 1. all write operations must be preceded by the sdp command sequence. ac write characteristics (1) ac write waveforms we controlled ce controlled 2-160 at28lv010
symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 100 ns t ds data set-up time 100 ns t dh data hold time 10 ns t wp write pulse width 200 ns t blc byte load cycle time 150 m s t wph write pulse width high 100 ns software protected write characteristics software protected program cycle waveforms (1, 2, 3) notes: 1. a0 - a14 must conform to the addressing sequence for the first 3-bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7 - a16) must be the same for each high to low transition of we (or ce). 3. oe must be high only when we and ce are both low. load last byte to last address (3) load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be re-activated at the end of program cycle. 3. 1 to 128-bytes of data are loaded. enter data protect state writes enabled (2) programming algorithm load data xx to any address (3) at28lv010 2-161
data polling waveforms symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns toggle bit characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. toggle bit waveforms 3. any address location may be used but the address should not vary. symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. 2-162 at28lv010
ordering information (1) t acc (ns) i cc (ma) ordering code package operation range active standby 200 15 0.2 AT28LV010-20jc 32j commercial AT28LV010-20pc 32p6 (0 to 70 c) AT28LV010-20tc 32t 15 0.2 AT28LV010-20ji 32j industrial AT28LV010-20pi 32p6 (-40 to 85 c) AT28LV010-20ti 32t 250 15 0.2 at28lv010-25jc 32j commercial at28lv010-25pc 32p6 (0 to 70 c) at28lv010-25tc 32t 15 0.2 at28lv010-25ji 32j industrial at28lv010-25pi 32p6 (-40 to 85 c) at28lv010-25ti 32t note: 1. see valid part number table below. package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 32p6 32 lead, 0.600" wide, plastic dual inline package (pdip) 32t 32 lead, plastic thin small outline package (tsop) valid part numbers the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28lv010 20 jc, ji, pc, pi, tc, ti at28lv010 25 jc, ji, pc, pi, tc, ti at28lv010 2-163
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